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FAN5009
Dual Bootstrapped 12V MOSFET Driver
Features
* Drives N-channel High-Side and Low-Side MOSFETs in a synchronous buck configuration * 12V High-Side and 12V Low-Side Drive * Internal Adaptive "Shoot-Through" Protection * Integrated Bootstrap Diode for High-Side Drive * Fast rise and fall times * Switching Frequency Up to 500kHz * OD input for Output Disable - allows for synchronization with PWM controller * SOIC-8 Package * Available in low thermal resistance MLP package
General Description
The FAN5009 is a dual, high frequency MOSFET driver, specifically designed to drive N-Channel power MOSFETs in a synchronous-rectified buck converter. These drivers, combined with a Fairchild Multi-Phase PWM controller and power MOSFETs, form a complete core voltage regulator solution for advanced microprocessors. The FAN5009 drives the upper and lower MOSFET gates of a synchronous buck regulator to 12VGS. The upper gate drive includes an integrated boot diode and requires only an external bootstrap capacitor (CBOOT). The output drivers in the FAN5009 have the capacity to efficiently switch power MOSFETs at frequencies up to 500kHz. The circuit's adaptive shoot-through protection prevents the MOSFETs from conducting simultaneously. The FAN5009 is rated for operation from 0C to +85C and is available in low-cost SOIC-8 or MLP packages.
Applications
* Multi-phase VRM/VRD regulators for Microprocessor Power * High Current/High Frequency DC/DC Converters * High Power Modular Supplies
Typical Application
12V
FAN5009
4
VCC
C VCC
1
BOOT Q1 C BOOT
PWM
2
8
HDRV SW Q2 L1 VOUT C OUT
OD
3
OVERLAP PROTECTION CIRCUIT
7
VCC
5
LDRV PGND
6
Figure 1. Typical Application.
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FAN5009
PRODUCT SPECIFICATION
Pin Configuration
Paddle (Ground) BOOT PWM OD VCC 1 2 3 4 FAN5009 8 7 6 5 HDRV SW PGND LDRV BOOT 1 PWM 2 OD 3 VCC 4 FAN5009 8 7 6 5 HDRV SW PGND LDRV
FAN5009M 8-pin SO-8 package
FAN5009MP 8-pin MLP package
(Paddle should be connected to ground or left floating)
Pin Definitions
Pin # Pin Name 1 2 3 4 5 6 7 8 BOOT PWM OD VCC LDRV PGND SW HDRV Pin Function Description Bootstrap Supply Input. Provides voltage supply to high-side MOSFET driver. Connect to bootstrap capacitor. See Applications Section. PWM Signal Input. This pin accepts a logic-level PWM signal from the controller. Output Disable. When low, this pin disables FET switching (HDRV and LDRV are held low). Power Input. +12V chip bias power. Bypass with a 1F ceramic capacitor. Low Side Gate Drive Output. Connect to the gate of low-side power MOSFET(s). Power ground. Connect directly to source of low-side MOSFET(s). Switch Node Input. Connect as shown in Figure 1. SW provides return for high-side bootstrapped driver and acts as a sense point for the adaptive shoot-thru protection. High Side Gate Drive Output - Connect to the gate of high-side power MOSFET(s).
Functional Block Diagram
4
VCC BOOT HDRV
OD PWM
2 3
1 8
+ 2.2 1.2
7
SW
1.2 VCC
5 6
LDRV PGND
2
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PRODUCT SPECIFICATION
FAN5009
Absolute Maximum Ratings
Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or other conditions beyond those indicated in the operational section of this specification is not implied. Exposure to the absolute maximum rating conditions for extended periods may affect device reliability. Absolute maximum ratings apply individually, not in combination. Unless otherwise specified, voltages are referenced to PGND. Parameter VCC to PGND PWM and OD pins SW to PGND BOOT to SW BOOT to PGND HDRV LDRV Continuous Transient ( t=200nsec)
Notes: 1. For transient derating beyond the levels indicated, refer to the graphs on page 7.
Min. -0.3 -0.3 Continuous Transient ( t=100nsec, F500kHz) Continuous Transient ( t=100nsec, F500kHz) VSW-1 -0.5 -2
(1)
Max. 15 5.5 15 25 15 30 33(1) VBOOT+0.3 VCC+0.3
Units V V V V V V V V V V
-1 -5(1) -0.3 -0.3
Thermal Information
Parameter Junction Temperature (TJ) Storage Temperature Lead Soldering Temperature, 10 seconds Vapor Phase, 60 seconds Infrared, 15 seconds Power Dissipation (PD) TA = 25C Thermal Resistance, SO8 - Junction to Case JC Thermal Resistance, SO8 - Junction to Ambient JA Thermal Resistance, MLP - Junction to Paddle JC 40 140 4 Min. 0 -65 Typ. Max. 150 150 300 215 220 715 Units C C C C C mW C/W C/W C/W
Recommended Operating Conditions
Parameter Supply Voltage VCC Ambient Temperature (TA) Junction Temperature (TJ) Conditions VCC to PGND Min. 10 0 0 Typ. 12 Max. 13.5 85 125 Units V C C
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FAN5009
PRODUCT SPECIFICATION
Electrical Specifications
VCC = 12V, and TA = 25C using circuit in Figure 2 unless otherwise noted. The * denotes specifications which apply over the full operating temperature range. Parameter Input Supply VCC Voltage Range VCC Current Bootstrap Diode Continuous Forward Current Reverse Breakdown Voltage Reverse Recovery Forward Voltage2 OD Input Input High Voltage Input Low Voltage Input Current Propagation Delay2 PWM Input Input High Voltage Input Low Voltage Input Current High-Side Driver Output Resistance, Sourcing Current Output Resistance, Sinking Current Transition Times2,4 Propagation Delay2,3 RHUP RHDN tR(HDRV) tF(HDRV) tpdh(HDRV) tpdl(HDRV) See Figure 2, and 4 VBOOT-VSW = 12V VBOOT-VSW = 12V See Figure 2 3.8 1.4 40 20 50 25 4.4 1.8 55 30 65 40 ns ns ns ns VIH(PWM) VIL(PWM) IIL(PWM) * * * -1 3.5 0.8 +1 V V A VIH (OD) VIL (OD) IOD tpdl(OD) tpdh(OD) OD = 3.0V See Figure 3 * * * -300 30 30 2.5 0.8 +300 40 45 V V nA ns ns Time2 IF(AVG) VR tRR VF IF = 10mA * * 15 10 0.8 0.95 25 mA V ns V VCC ICC OD = 0V * * 6.4 12 3.5 13.5 8 V mA Symbol Conditions Min. Typ. Max. Units
12V 33K
FAN5009
1 BOOT 2 PWM 3 OD HDRV 8 SW 7 PGND 6 LDRV 5 3000pf 3000pf
10K
4 VCC 1f
Figure 2. Test Circuit
4
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PRODUCT SPECIFICATION
FAN5009
Electrical Specifications (continued)
Parameter Low-Side Driver Output Resistance, Sourcing Current Output Resistance, Sinking Current Transition Times2,4 Propagation Delay2,3 RLUP RLDN tR(LDRV) tF(LDRV) tpdh(LDRV) tpdl(LDRV) tpdh(ODRV) See Adaptive Gate Drive Circuit description See Figures 2, 4 See Figure 2 3.4 1.4 40 20 20 25 240 4.0 1.8 50 30 30 40 ns ns ns ns ns Symbol Conditions Min. Typ. Max. Units
NOTES: 1. All limits at operating temperature extremes are guaranteed by design, characterization and statistical quality control 2. AC Specifications guaranteed by design/characterization (not production tested). 3. For propagation delays, "tpdh" refers to low-to-high signal transition and "tpdl" refers to high-to-low signal transition 4. Transition times are defined for 10% and 90% of DC values
VIH(OD)
OD
VIL(OD) t pdl(OD) tpdh(OD)
LDRV / HDRV
Figure 3. Output Disable Timing
VIH(PWM)
PWM
t pdl (LDRV)
VIL(PWM)
LDRV
1.2V
t pdh(HDRV)
t pdl (HDRV)
HDRV-SW
t pdh(LDRV)
SW
2.2V
Figure 4. Adaptive Gate Drive Timing REV. 1.0.5 7/22/04
5
FAN5009
PRODUCT SPECIFICATION
Typical Characteristics
Gate Drive Rise and Fall Times
PWM PWM HDRV HDRV
LDRV
LDRV
HDRV Rise/Fall Times vs. CLOAD
70 60 50
TRISE
LDRV Rise/Fall Times vs. CLOAD
70 60
Time (nsec)
50 40 30
Time (nsec)
TRISE
40 30 20
TFALL
TFALL
20 10 0 1,000
10 0 1,000
2,000
3,000
4,000
5,000
2,000
3,000
4,000
5,000
CLOAD (pF)
CLOAD (pF)
HDRV Impedance vs. Temperature (normalized)
1.5 1.4
LDRV Impedance vs. Temperature (normalized)
1.5 1.4
Z (normalized)
1.3 1.2 1.1 1.0 0.9 0.8 0 25 50 75 100 125
Source Sink
Z (normalized)
1.3 1.2 1.1 1.0 0.9 0.8 0 25 50 75 100 125
Source Sink
Temperature (C)
Temperature (C)
6
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PRODUCT SPECIFICATION
FAN5009
Typical Characteristics (continued)
ICC vs. Frequency
20 1,600 1,400 1,200
Boot Diode VF vs. IF
16
ICC (mA)
12
VF (mV)
1,000 800 600 400
25C 85C 125C
8
4
0 0 100 200 300 400 500
1
10
100
1000
Frequency (KHz)
IF (mA)
Negative SW Voltage Transient
-13 -12 -11 -10 10 9 8 7
Boot Diode Peak IF
Peak I F (A)
0 100 200 300 400 500
VSW (V)
-9 -8 -7 -6 -5 -4 -3
6 5 4 3 2 1 0 50 75 100 125 150 175 200
Transient Duration (nsec)
ton at 500KHz (nsec)
Negative LDRV Voltage Transient
-6.0 -5.0 -4.0 -3.0 ~1.2J per cycle -2.0 -1.0 0.0 0 100 200 300 400 500 36 35
Boot Voltage Transient
VBOOT-GND (V)
VLDRV (V)
34 33 32 31 30 0 100 200 300 400 500
Transient Duration (nsec)
Transient Duration (nsec)
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FAN5009
PRODUCT SPECIFICATION
Circuit Description
The FAN5009 is a dual MOSFET driver optimized for driving N-channel MOSFETs in a synchronous buck converter topology. A single PWM input signal is all that is required to properly drive the high-side and the low-side MOSFETs. Each driver is capable of driving a 3nF load at speeds up to 500kHz. For a more detailed description of the FAN5009 and its features, refer to the Internal Block Diagram and Figure 1.
Once the LDRV pin is discharged below ~1.2V, Q1 begins to turn ON after adaptive delay tpdh(HDRV). To preclude overlap during the high-to-low transition (Q1 OFF to Q2 ON), the adaptive circuitry monitors the voltage at the SW pin. When the PWM signal goes LOW, Q1 will begin to turn OFF after some propagation delay (tpdl(HDRV)). Once the SW pin falls below ~2.2V, Q2 begins to turn ON after adaptive delay tpdh(LDRV). Additionally, VGS of Q1 is monitored. When VGS(Q1) is discharged below ~1.2V, a secondary adaptive delay is initiated, which results in Q2 being driven ON after tpdh(ODRV), regardless of SW state. This function is implemented to ensure CBOOT is recharged each switching cycle, particularly for cases where the power convertor is sinking current and SW voltage does not fall below the 2.2V adaptive threshold. Secondary delay tpdh(ODRV) is longer than tpdh(LDRV).
Low-Side Driver
The low-side driver (LDRV) is designed to drive a groundreferenced low RDS(on) N-channel MOSFETs. The bias for LDRV is internally connected between VCC and PGND. When the driver is enabled, the driver's output is 180 out of phase with the PWM input. When the FAN5009 is disabled (OD = 0V), LDRV is held low.
High-Side Driver
The high-side driver (HDRV) is designed to drive a floating N-channel MOSFET. The bias voltage for the high-side driver is developed by a bootstrap supply circuit, consisting of the internal diode and external bootstrap capacitor (CBOOT) . During start-up, SW is held at PGND, allowing CBOOT to charge to VCC through the internal diode. When the PWM input goes high, HDRV will begin to charge the high-side MOSFET's gate (Q1). During this transition, charge is removed from CBOOT and delivered to Q1's gate. As Q1 turns on, SW rises to VIN, forcing the BOOT pin to VIN +VC(BOOT), which provides sufficient VGS enhancement for Q1. To complete the switching cycle, Q1 is turned off by pulling HDRV to SW. CBOOT is then recharged to VCC when SW falls to PGND. HDRV output is in phase with the PWM input. When the driver is disabled, the high-side gate is held low.
Application Information
Supply Capacitor Selection
For the supply input (VCC) of the FAN5009, a local ceramic bypass capacitor is recommended to reduce the noise and to supply the peak current. Use at least a 1F, X7R or X5R capacitor. Keep this capacitor close to the FAN5009 VCC and PGND pins.
Bootstrap Circuit
The bootstrap circuit uses a charge storage capacitor (CBOOT) and the internal diode, as shown in Figure 1. Selection of these components should be done after the high-side MOSFET has been chosen. The required capacitance is determined using the following equation:
QG C BOOT = --------------------V BOOT (1)
Adaptive Gate Drive Circuit
The FAN5009 embodies an advanced design that ensures minimum MOSFET dead-time while eliminating potential shoot-through (cross-conduction) currents. It senses the state of the MOSFETs and adjusts the gate drive, adaptively, to ensure they do not conduct simultaneously. Refer to Figure 4 for the relevant timing waveforms. To prevent overlap during the low-to-high switching transition (Q2 OFF to Q1 ON), the adaptive circuitry monitors the voltage at the LDRV pin. When the PWM signal goes HIGH, Q2 will begin to turn OFF after some propagation delay (tpdl(LDRV)).
where QG is the total gate charge of the high-side MOSFET, and VBOOT is the voltage droop allowed on the high-side MOSFET drive. For example, the QG of the FDD6696 is about 35nC @ 12VGS. For an allowed droop of ~300mV, the required bootstrap capacitance is 100nF. A good quality ceramic capacitor must be used. The average diode forward current, IF(AVG), can be estimated by:
I F ( AVG ) = Q GATE x F SW (2)
where FSW is the switching frequency of the controller. The peak surge current rating of the internal diode should be checked in-circuit, since this is dependent on the equivalent impedance of the entire bootstrap circuit, including the PCB traces. For applications requiring higher IF, an external diode may be used in parallel to the internal diode.
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PRODUCT SPECIFICATION
FAN5009
Thermal Considerations
Total device dissipation:
P D = P Q + P R + P HDRV + P LDRV (3)
where PQ represents quiescent power dissipation:
P Q = V CC x [ 4mA + 0.036 ( F SW - 100 ) ] (4)
RG is the polysilicon gate resistance, internal to the FET. RE is the external gate drive resistor implemented in many designs. Note that the introduction of RE can reduce driver power dissipation, but excess RE may cause errors in the "adaptive gate drive" circuitry. For more information please refer to Fairchild app note AN-6003, "Shoot-through" in Synchronous Buck Converters. PLDRV is dissipation of the lower FET driver.
P LDRV = P L ( R ) + P L ( F ) (11)
where FSW is switching frequency (in kHz). PR is power dissipated in the bootstrap rectifier:
P R = V F x F SW x Q G1 (5)
Where PH(R) and PH(F) are internal dissipations for the rising and falling edges, respectively:
R LUP P L ( R ) = P Q2 x --------------------------------------R LUP + R E + R G R LDN P L ( F ) = P Q2 x ---------------------------------------R HDN + R E + R G (12)
Where QG1 is total gate charge of the upper FET (Q1) for it's applied VGS. VF for the applied IF(AVG) can be graphically determined using the datasheet curves, where:
I F ( AVG ) = F SW x Q G1 (6)
(13)
where:
1 P Q2 = -- x Q G2 x V GS ( Q2 ) x F SW 2 (14)
PHDRV represents internal power dissipation of the upper FET driver.
P HDRV = P H ( R ) + P H ( F ) (7)
Layout Considerations
Use the following general guidelines when designing printed circuit boards (see Figures 6 and 7): 1. Trace out the high-current paths and use short, wide (>25 mil) traces to make these connections. Connect the PGND pin of the FAN5009 as close as possible to the source of the lower MOSFET. The VCC bypass capacitor should be located as close as possible to VCC and PGND pins. Use vias to other layers when possible to maximize thermal conduction away from the IC.
Where PH(R) and PH(F) are internal dissipations for the rising and falling edges, respectively:
R HUP P H ( R ) = P Q1 x ---------------------------------------R HUP + R E + R G R HDN P H ( F ) = P Q1 x ---------------------------------------R HDN + R E + R G (8)
2.
(9)
3. 4.
where:
1 P Q1 = -- x Q G1 x V GS ( Q1 ) x F SW 2 (10)
As described in eq. 8 and 9 above, the total power consumed in driving the gate is divided in proportion to the resistances in series with the MOSFET's internal gate node as shown below:
BOOT Q1 R HUP
HDRV RE
G
CBOOT
1 2 3 8 7 6 5
RG
4
S
R HDN
SW
CVCC
Figure 6. External component placement recommendation for SO8 package (not to scale)
Figure 5. Driver dissipation model
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FAN5009
PRODUCT SPECIFICATION
5.
The paddle on the MLP package is internally referenced to ground. It can be left floating or connected to ground. For best thermal performance it should be connected to ground as shown in Figure 7.
CBOOT
1 2 3 4 8 7 6 5
PADDLE
CVCC
VIAS GROUND
Figure 7. Recommended layout for MLP package. Also accepts SO8 package (not to scale)
6.
The recommended land pattern shown in the MLP mechanical dimensions will work with both MLP-8 and SO-8 packages.
The circuit in Figure 1 illustrates a typical implementation of a single phase of a multi-phase buck converter for VCORE applications. For a complete VR10 design example, please refer to the FAN5019 or FAN5018 datasheets.
10
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PRODUCT SPECIFICATION
FAN5009
Mechanical Dimensions
0.150, 8 Lead SOIC Package
Symbol A A1 B C D E e H h L N ccc Inches Min. Max. Millimeters Min. Max. Notes: Notes 1. Dimensioning and tolerancing per ANSI Y14.5M-1982. 2. "D" and "E" do not include mold flash. Mold flash or protrusions shall not exceed .010 inch (0.25mm). 3. "L" is the length of terminal for soldering to a substrate. 4. Terminal numbers are shown for reference only. 5 2 2 5. "C" dimension does not include solder finish thickness. 6. Symbol "N" is the maximum number of terminals.
.053 .069 .004 .010 .013 .020 .0075 .010 .189 .197 .150 .158 .050 BSC .228 .010 .016 8 0 -- 8 .004 .244 .020 .050
1.35 1.75 0.10 0.25 0.33 0.51 0.20 0.25 4.80 5.00 3.81 4.01 1.27 BSC 5.79 0.25 0.40 8 0 -- 8 0.10 6.20 0.50 1.27
3 6
8
5
E
H
1
4
D A1 A SEATING PLANE B -C- LEAD COPLANARITY ccc C
h x 45 C
e
L
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FAN5009
PRODUCT SPECIFICATION
Mechanical Dimensions
5mm x 6mm, 8 Lead MLP Package
5.0 A B 4.50
6.0
3.50 4.25
6.25
0.25 2X
C
(1.00)
0.25 2X
C
TOP VIEW
1.27 TYP
0.65 TYP
LAND PATTERN RECOMMENDATION
0.10 C (0.25) 1.0 MAX 0.08 C 0.05 0.00
SIDE VIEW
4.25 A 1.75 1 2 3 4
C SEATING PLANE
PIN #1 IDENT. (OPTIONAL)
0.75 A 0.35
3.25 A 1.25
NOTES: A) B) C)
DOES NOT FULLY CONFORM TO JEDEC REGISTRATION MO-229, DATED 11/2001. DIMENSIONS ARE IN MILLIMETERS. DIMENSIONING AND TOLERANCES PER ASME Y14.5-1994.
8 1.27
7
6
5
0.28-0.40 A 0.10 M C A B
3.81 A
0.05 M C
BOTTOM VIEW
12
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FAN5009
PRODUCT SPECIFICATION
Ordering Information
Part Number FAN5009M FAN5009MX FAN5009MPX Temperature Range 0C to 85C 0C to 85C 0C to 85C Package SOIC-8 SOIC-8 MLP-8 Packing Rails Tape and Reel Tape and Reel
DISCLAIMER FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS. LIFE SUPPORT POLICY FAIRCHILD'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury of the user. www.fairchildsemi.com
7/22/04 0.0m 001 Stock#DS505009 2004 Fairchild Semiconductor Corporation
2. A critical component in any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness.

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